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A Highly Linear and Efficient Differential CMOS Power Amplifier With Harmonic Cont
一款2.45 GHz高线性度与高效率的差分CMOS功率放大器，采用谐波终止技术提升性能。
20.5 dBm输出功率, 17.5 dB增益, 37% PAE, IMD3 <45 dBc, IMD5 <57 dBc
CMOS功率放大器谐波终止线性度高效率2.45 GHz
▸创新点1：谐波终止技术提升线性度 - 通过源极谐波终止和漏极谐波终止的协同设计，有效抑制二次谐波，使IMD3和IMD5分别最大改善6 dB和7 dB，显著提升PA线性度（方法创新）
▸创新点2：差分结构优化效率 - 采用全差分CMOS架构结合最优栅极偏置，实现37%的功率附加效率（PAE）和17.5 dB功率增益，在2.45 GHz频段达成高效率与高增益的平衡（电路创新）
▸创新点3：集成化设计减少外部组件 - 除输出变压器和少量键合线外，所有两级电路元件均集成于单一芯片，通过0.18μm Cu-metal CMOS工艺实现高度集成，降低系统复杂度（系统创新）
▸创新点4：宽功率范围内的线性度维持 - 在输出功率回退5 dB时仍保持IMD3<-45 dBc和IMD5<-57 dBc的线性性能，且OFDM测试中EVM改善40%以上，满足4.6% EVM标准（性能创新）
Abstract
A 2.45 GHz fully differential CMOS power amplifier
(PA) with high efficiency and linearity is presented. For this work,
a 0.18-
m standard CMOS process with Cu-metal is employed
and all components of the two-stage circuit except an output
transformer and a few bond wires are integrated into one chip.
To improve the linearity, an optimum gate bias is applied for the
cancellation of the nonlinear harmonic generated by
/51and a
new harmonic termination technique at the common source node
is adopted