JSSC 2006第6期Clocking & PLLs0.35μm CMOSDLL

All-Digital Delay-Locked LoopPulsewidth-Control Loop With Adjustable Duty Cycles

提出全数字延迟锁定环和脉宽控制环，支持可调占空比，无需输入时钟50%占空比。

DLL: 140-260MHz, 25%/50%/75%占空比; PWCL: 400-600MHz, 30%-70%占空比(步进10%)

全数字延迟锁定环脉宽控制环可调占空比时间数字转换CMOS工艺

▸采用闪存时间数字转换确保相位对齐和占空比

▸采用顺序时间数字转换减少D触发器数量

▸消除输入时钟50%占空比要求

Abstract

An all-digital delay-locked loop (DLL) and an all-dig- ital pulsewidth-control loop (PWCL) with adjustable duty cycles are presented. For the DLL, by using the ﬂash time-to-digital conversion, both the phase alignment and the duty cycle of the output clock are assured in 10 cycles. For the PWCL, the sequen- tial time-to-digital conversion is adopted to reduce the required D-ﬂip-ﬂops and lock within 28 cycles. For both of the proposed circuits, the requirement of the input clock with 50% duty cyc