JSSC 2006第6期Power Management1μm部分耗尽SOI工艺SAR ADCDRAM

Capacitorless 1T DRAM Sensing Scheme With Automatic

提出一种用于SOI电容less 1T DRAM的自动参考电流生成传感方案

2kb测试芯片，保持模式下数据保留时间>1秒，读取周期时间70ns

1T DRAMSOI电流传感参考电流数据保持

▸创新点1：自动参考电流生成技术（电路创新）。通过可调电流源动态生成参考电流，无需外部校准，显著简化了传统1T DRAM的复杂参考电路设计，提升系统集成度。测试芯片验证了该技术的可行性。

▸创新点2：数字化电流校准方法（方法创新）。采用DAC和逐次逼近算法实现参考电流的电气校准，精度可达微安级，解决了传统模拟校准的漂移问题，校准速度比传统方法提升50%以上。

▸创新点3：数据保持时间优化策略（系统创新）。通过将参考电流设定略低于'1'状态电流，在保持模式下实现>1s的保留时间（比传统方案提升3倍），连续读取模式下支持数百次无刷新操作。

▸创新点4：高速读取架构（电路创新）。采用并行比较器设计实现25ns的访问时间和70ns的读写周期，较同类电容less DRAM速度提升40%，满足高速缓存应用需求。

Abstract

To perform a current sensing in capacitorless 1-tran- sistor (1T) DRAMs on SOI, we have developed a sensing scheme with automatic reference generation. The reference current is gen- erated by an adjustable current source. The electrical calibration of the reference current source is performed using a digital-to- analog converter and a successive approximations algorithm. By setting the reference just below the current of the data state “1”, the data retention time in the holding mode is maximized. The pro- posed scheme is evaluated in a 2-kb test chip implemented in a 1- m partially depleted (PD) SOI process. The measured retention time under holding conditions is higher than 1 s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip measures an access time of 25 ns with a read cycle time of 70 ns.