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High Performance Asynchronous Design Using Single-Track Full-Buffer Standard Cel
提出高性能异步设计模板STFB，实现接近全定制性能的标准单元设计流程。
TSMC 0.25μm工艺, 260k晶体管, 1.45GHz吞吐量
异步设计单轨全缓冲标准单元前缀加法器自动布局布线
▸采用单轨全缓冲(STFB)模板实现高性能异步设计
▸通过标准单元设计流程和行业标准CAD工具实现自动化布局布线
▸相比QDI模板吞吐量提升三倍且面积减半
Abstract
This paper presents a high-performance asyn-
chronous template, single-track full-buffer (STFB), which
achieves close to full-custom performance using a standard cell de-
sign flow and industry standard CAD tools to perform schematic
capture, simulation, cell layout, and automatic placement and
routing. This template and flow is demonstrated and evaluated
with the implementation of a 64-bit asynchronous prefix adder,
and its test circuitry, using the TSMC 0.25-
m process. The 64-bit
asynchronous pr