JSSC 2006第6期Clocking & PLLs0.18-m/0.13-mPLLClock Generation

JUNE 2006 VOLUME 41 NUMBER 6 IJSCBC ISSN 0018-9200 EDITORIAL New Associate Edito

该期刊包含多篇关于CMOS工艺下锁相环、频率合成器和时钟生成器的设计论文。

0.18-m CMOS, 1-V, 24-GHz, 17.5-mW

锁相环频率合成器CMOS时钟生成器毫米波

▸1-V 24-GHz 17.5-mW Phase-Locked Loop

▸DLL-Based Frequency Synthesizer for UWB

▸Millimeter-Wave VCOs in 0.13-m CMOS

Abstract

REGULAR PAPERS A 1-V 24-GHz 17.5-mW Phase-Locked Loop in a 0.18- m CMOS Process .................................................. ................................................. A. W . L. Ng, G. C. T . Leung, K.-C. Kwok, L. L. K. Leung, and H. C. Luong 1236 The Design and Analysis of a DLL-Based Frequency Synthesizer for UWB Application .. ... T.-C. Lee and K.-J. Hsiao 1245 The Design and Analysis of a Miller-Divider-Based Clock Generator for MBOA-UWB Application .. .................... ....