Low-Power Logic Circuit and SRAM Cell Applications With Silicon on Depletion Layer CMOS (SODEL CMOS) Technology

Abstract

In this paper, the switching performance of Silicon on Depletion Layer CMOS (SODEL CMOS) [1] is investigated with a view to realizing high-speed and low-power CMOS applications. Thanks to smaller parasitic capacitance, the propagation delay time /40 /112/100/41in SODEL CMOS has been improved by up to 25% compared to that of conventional bulk CMOS in five stacked nFET inverters at the same /100/100. It is also confirmed that about 30% better power-delay product can be realized at the same /112/100 with reduced /100/100in SODEL CMOS. In SRAM cell applications, SODEL CMOS shows high Static Noise Margin (SNM) of 95 mV at /100/100/61/48 /54V. Smaller bit- line delay is expected and confirmed in SODEL CMOS SRAM by SPICE simulations. Latch-up immunity for -particle irradiation in SODEL CMOS was also found to be comparable to that of con- ventional bulk CMOS. Therefore, SODEL CMOS device and cir- cuit technology is expected to provide a better solution for low- power system-on-a-chip (SoC).