← 返回 JSSC 论文列表JSSC 2006第7期Data Converters0.13μmPipeline ADC
A 10-bit 400-MSs 160-mW 013- 22m CMOS Dual-Channel Pipeline ADC Without Channel
一款无需通道校准的10位400MS/s双通道流水线ADC，采用自适应闭环采样技术
10-bit 400-MS/s 160-mW 0.13-μm CMOS
双通道ADC流水线结构自适应采样增益失配时钟偏移
▸创新点1：自适应闭环采样技术消除通道偏移（方法创新）。通过多级放大器构建的闭环反馈系统动态调整采样参数，有效消除通道间偏移误差，实测偏移失配小于0.1%，无需额外校准电路。
▸创新点2：多级高增益放大器设计（电路创新）。采用级联放大器结构实现>100dB的DC增益，在1.2V低电源电压下保持大信号摆幅，将通道间增益失配控制在0.2%以内。
▸创新点3：单时钟边沿采样方案（系统创新）。通过同步化双通道的采样时钟触发边沿，将时钟偏差降低至皮秒级，在400MS/s高速采样下实现29MHz输入信号的54.8dB SNDR。
▸创新点4：混合架构优化（系统创新）。结合流水线与时间交织技术，在0.13μm CMOS工艺下实现4.2mm²面积效率，功耗仅160mW，较同类设计降低20%以上。
Abstract
This paper describes a 10-bit 400-MS/s dual-channel
analog-to-digital converter (ADC) insensitive to offset, gain,
and sampling-time mismatches between channels. An adaptive
closed-loop sampling technique based on a multi-stage amplifier
eliminates the channel offset effectively. Multi-stage amplifiers
with high DC gain reduce the gain mismatch between channels
and guarantee a large signal swing at low supply voltages. A
single clock-edge sampling scheme for clock-skew reduction
minimizes the samp