A High-Speed 850-nm Optical Receiver Front-End in 0.18-/22m CMOS

Abstract

A high-speed optical interface circuit for 850-nm op- tical communication is presented. Photodetector, transimpedance amplifier (TIA), and post-amplifier are integrated in a standard 0.18- m 1.8-V CMOS technology. To eliminate the slow substrate carriers, a differential n-well diode topology is used. Device simu- lations clarify the speed advantage of the proposed diode topology compared to other topologies, but also demonstrate the speed–re- sponsivity tradeoff. Due to the lower responsivity, a very sensi- tive transimpedance amplifier is needed. At 500 Mb/s, an input power of 8 dBm is sufficient to have a bit error rate of/51 /49/48 /49/48. Next, the design of a broadband post-amplifier is discussed. The small-signal frequency dependent gain of the traditional and mod- ified Cherry–Hooper stage is analyzed. To achieve broadband op- eration in the output buffer, so-called “ doublers” are used. For a differential 10 mV/112/112/50/51/49 /49pseudo random bit sequence, a bit error rate of /53 /49/48 /49/50at 3.5 Gb/s has been measured. At lower bit-rates, the bit error rate is even lower: a 1-Gb/s 10-mV/112/112input signal results in a bit error rate of /55 /49/48 /49/52. The TIA consumes 17 mW, while the post-amplifier circuit consumes 34 mW.