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Dynamic State-Retention Flip-Flop for Fine-Grained Power Gating With Small Desig
提出一种基于感测放大器的动态状态保持触发器，用于细粒度电源门控以减少待机功耗。
100 ps to 200 ps D-to-Q delays, milliseconds retention time
动态状态保持触发器细粒度电源门控感测放大器待机功耗标准设计流程
▸无需额外控制信号或电源即可实现状态保持
▸适用于短时空闲电路的细粒度电源门控
▸可集成到标准设计流程中无需修改
Abstract
Fine-grained power gating is the rigorous application
of sleep transistor scheme to reduce stand-by power consumption
in idle circuit blocks. Small circuit blocks are suspended for a
short time while they are temporarily not needed. A sense-ampli-
fier-based state retention flip-flop is proposed, that preserves the
logical state of the circuit during these short idle periods. This dy-
namic state retention flip-flop requires neither additional control
signals nor an additional power supply for its st