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Low Leakage Techniques for FPGAs Andrea Lodi Luca Ciccarelli and Roberto Guerrie
研究FPGA在90nm及以下工艺中的低泄漏技术，实现86%待机能耗节省和46%动态泄漏降低。
86% stand-by energy saving, 46% active leakage reduction, 3% area increase
FPGA低泄漏技术无线应用开关块查找表
▸应用多种低泄漏技术于FPGA设计
▸优化开关块和查找表以减少泄漏
▸保持延迟不变同时仅增加3%面积
Abstract
Reconfigurable architectures are well suited for wire-
less applications since they provide high performance computation
together with the capability to adapt to changing communication
protocols. Moving to 90-nm technology and below, FPGAs could
suffer from leakage energy consumption due to the large number
of inactive transistors. This paper presents an extensive study on
the application of different low-leakage techniques to the design of
FPGAs. The approaches are compared and mixed to find an i