Low Leakage Techniques for FPGAs Andrea Lodi, Luca Ciccarelli, and

Abstract

Reconfigurable architectures are well suited for wire- less applications since they provide high performance computation together with the capability to adapt to changing communication protocols. Moving to 90-nm technology and below, FPGAs could suffer from leakage energy consumption due to the large number of inactive transistors. This paper presents an extensive study on the application of different low-leakage techniques to the design of FPGAs. The approaches are compared and mixed to find an im- plementation of switch blocks and look-up tables which reduces leakage without affecting delay and area. The circuits we propose achieve an 86% stand-by energy saving and 46% active leakage reduction with respect to standard implementations. The FPGA delay is not affected, while area is increased by only 3%.