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JSSC 2006第8期Other

3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-V

探讨硅通孔技术在三维集成和硅封装中的应用及其性能优势
50μm间距互连,16倍标准芯片I/O提升
硅通孔三维集成系统级封装高密度互连硅载体封装
创新点1:硅通孔技术(TSV)作为三维集成的关键方法创新,通过垂直互连实现芯片间高密度电气连接,相比传统引线键合技术,显著减少互连长度(50μm间距),提升信号传输速度并降低功耗。
创新点2:三维集成技术通过芯片堆叠或硅基硅集成(如3D IC、硅中介层),实现系统级创新,将异构芯片(如逻辑与存储)垂直整合,带宽提升16倍,同时支持已知良品晶圆(KGD)测试以提高良率。
创新点3:高密度互连技术结合硅载体封装,提供20-100倍于传统有机/陶瓷基板的布线密度,集成高性能无源器件(如去耦电容),优化模块架构,降低系统级噪声与延迟。
创新点4:硅中介层集成功能(如去耦电容)作为电路创新,替代片外分立元件,减少封装面积并改善电源完整性,适用于光电子收发器等高性能应用。
Abstract
System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on ap- plication needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two- and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing applica- tions. This paper will discuss a few emerging technologies which offer opportunities