JSSC 2006第8期RF & Wireless0.35μm BiCMOSPipeline ADC

A 14-bit 125 MSs IFRF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter

一款14位125MS/s无采样保持放大器的流水线ADC，具有100dB SFDR和50fs抖动。

14-bit, 125MS/s, 100dB SFDR, 50fs jitter, 0.35μm BiCMOS

流水线ADC无采样保持放大器时钟抖动优化高动态范围射频采样

▸集成采样保持电路于第一级流水线，无需专用SHA

▸采用新型抖动仿真技术优化时钟抖动

▸首次实现14位精度且输入频率达500MHz

Abstract

This paper describes a 14-bit, 125 MS/s IF/RF sam- pling pipelined A/D converter (ADC) that is implemented in a 0.35 m BiCMOS process. The ADC has a sample-and-hold circuit that is integrated in the ﬁrst pipeline stage, which re- moves the need for a dedicated sample-and-hold ampliﬁer (i.e., “SHA-less”). It also has a sampling buffer that is turned off during the hold clock phases to save power. To accurately estimate and minimize the clock jitter, a new jitter simulation technique was used whos