← 返回 JSSC 论文列表JSSC 2006第8期Wireline I/O0.25μmEqualizer
A 25- to 35-Gbs Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay
一种采用连续时间宽带宽延迟线的自适应FIR均衡器，适用于2.5至3.5Gb/s数据通信。
0.25μm CMOS, 2.5V, 2.5Gb/s时95mW功耗
自适应均衡器FIR滤波器连续时间延迟线分数间隔结构脉冲提取
▸采用分数间隔结构实现宽带宽
▸提出带主动电感负载设计的反相器作为延迟单元
▸低功耗且面积高效的脉冲提取方法用于闭环自适应
Abstract
This paper presents an adaptive finite impulse re-
sponse (FIR) equalizer with continuous-time wide-bandwidth
delay line in CMOS 0.25-
m process for 2.5-Gb/s to 3.5-Gb/s data
communications. To achieve wide bandwidth, fractionally spaced
structure is used and an inverter with active-inductor load design
is proposed as the delay cell of the tap delay line. Close loop adap-
tation of the fractionally spaced FIR equalizer is demonstrated
using a low-power and area-efficient pulse extraction method
as