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A Digital Clock and Data Recovery Architecture for Multi-Gigabits Binary Links
提出一种用于高速二进制链路的数字时钟和数据恢复架构，替代传统模拟PLL中的模拟滤波器和压控振荡器。
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数字时钟恢复数据恢复高速二进制链路bang-bang相位检测器数字CDR
▸数字组件替代模拟滤波器和VCO
▸线性化分析bang-bang相位检测器
▸测量并分析数字CDR系统的极限周期行为
Abstract
In this tutorial paper, we present a general architec-
ture for digital clock and data recovery (CDR) for high-speed bi-
nary links. The architecture is based on replacing the analog loop
filter and voltage-controlled oscillator (VCO) in a typical analog
phase-locked loop (PLL)-based CDR with digital components. We
provide a linearized analysis of the bang-bang phase detector and
CDR loop including the effects of decimation and self-noise. Ad-
ditionally, we provide measured results from an imple