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A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs
一款高集成度CMOS模拟基带收发器，包含13位180MSPS流水线ADC和双12位180MSPS电流导向DAC。
13-bit 180MSPS ADC, 12-bit 180MSPS DAC, 10.6 ENOB at 15MHz, 9.7 ENOB at 100MHz, >62dB SFDR
CMOS模拟基带ADCDAC流水线
▸无专用跟踪保持级的ADC设计
▸采用前端2.5位级与匹配MDAC/比较器跟踪电路
▸动态线性增强架构的DAC
Abstract
A CMOS analog baseband transceiver with a 13-bit, 180 MSPS pipelined ADC and dual 12-bit, 180 MSPS current-steering DACs is presented. The ADC is implemented without a dedicated track-and-hold stage, utilizes a front-end 2.5-bit stage with matched MDAC/comparator tracking circuits, and demonstrates an ENOB of 10.6 bits at 15 MHz and 9.7 bits at 100 MHz, employing a low-jitter delay-lock loop for its phasing. The dual I/Q DACs show over 62 dB SFDR over the Nyquist band by utilizing a dynamic linearity enhancing architecture.