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JSSC 2006第9期RF & Wireless0.13μmDAC

1.2-V Low-Power Multi-Mode DAC+Filter Blocks for Reconfigurable (WLAN/UMTS, WLAN/Bluetooth) Transmitters Nicola Ghittori, Andrea Vigna, Piero Malcovati, Stefano D’Amico, and

采用0.13μm CMOS工艺实现的可编程DAC-滤波器模块,支持WLAN/UMTS/蓝牙多标准切换。
1.2V, 100MHz(WLAN)/50MHz(UMTS/蓝牙), 8mW(WLAN)/5.4mW(蓝牙), OIP3>28dBm
数模转换器重构滤波器多标准收发机低功耗设计CMOS工艺
数字可编程DAC转换频率和滤波器截止频率
多模式低功耗设计(WLAN/UMTS/蓝牙)
单1.2V电源供电的宽带高性能实现
Abstract
Two versions of a baseband block composed by a 8-bit current-steering DAC and a fourth-order low-pass reconstruction filter are realized in a 0.13- m CMOS technology to be embedded in multistandard wireless transmitters. In order to satisfy the specifications of WLAN IEEE 802.11a/b/g, UMTS, and Bluetooth standards, the proposed devices can be digitally programmed, adjusting the DAC conversion frequency and the low-pass filter cut-off frequency. For the WLAN case, the DAC operating fre- quency and the filter bandwidth are set to 100 MHz and 11 MHz, respectively, for the UMTS case, they are equal to 50 MHz and 2.5 MHz, and for the Bluetooth case, they are equal to 50 MHz and 1 MHz. The first device is reconfigurable between WLAN and UMTS, and the second one between WLAN and Bluetooth. The two fabricated devices operate from a single 1.2-V supply voltage and occupy a 0.8 mm /50and 0.7 mm/50die area, respectively. The power consumption is optimized according to the operation mode and is 8 mW in WLAN mode, 8.4 mW in UMTS mode, and 5.4 mW in Bluetooth mode. For all the considered standards, the measured OIP3 is larger than 28 dBm, while the SFDR is 54 dB for WLAN, 61 dB for UMTS, and 63 dB for Bluetooth.