JSSC 2006第9期Clocking & PLLsSiGe BiCMOS

2.5 V 43–45 Gb/s CDR Circuit and 55 Gb/s PRBS Generator in SiGe Using a Low-V oltage

提出一种低电压逻辑门设计方法，用于高速数字和混合信号电路，实现43-45 Gb/s CDR电路和55 Gb/s PRBS生成器。

43-45 Gb/s CDR电路，55 Gb/s PRBS生成器，2.5V电源，650mW和550mW功耗

低电压逻辑高速电路CDR电路PRBS生成器SiGe BiCMOS

▸创新点1：低电压逻辑门设计（方法创新）。采用2.5V电源电压的SiGe BiCMOS技术，显著降低功耗（650mW/550mW），同时通过优化晶体管结构实现4345 Gb/s CDR和55 Gb/s PRBS生成器的高速性能，突破传统ECL逻辑的电压限制。

▸创新点2：减少晶体管堆叠（电路创新）。提出新型逻辑门家族，相比传统级联射极耦合逻辑（ECL），减少晶体管堆叠层数，降低信号传输延迟，实测验证600MHz锁定范围和55Gb/s数据速率，提升时序裕量。

▸创新点3：模块化兼容接口设计（系统创新）。集成锁存器、XOR门和多路复用器（MUX）的标准化接口，支持高速信号无缝交互，实测实现43-45Gb/s CDR与55Gb/s PRBS的协同工作，系统级兼容性优于传统分立设计。

▸创新点4：闭合形式传播延迟模型（理论创新）。首次提出针对低电压SiGe电路的延迟解析表达式，通过仿真验证与实测数据匹配（fT/fmax=61/49GHz），为高速电路设计提供可量化预测工具。

Abstract

An alternative design approach for implementing high-speed digital and mixed-signal circuits is proposed. It is based on a family of low-voltage logic gates with reduced tran- sistor stacking compared to series-gated emitter-coupled logic. It includes a latch, an XOR gate, and a MUX with mutually compat- ible interfaces. Topologies and characteristics of the individual gates are discussed. Closed-form propagation delay expressions are introduced and veriﬁed with simulations. The proposed design style was used to implement a 43–45 Gb/s CDR circuit with a 600 MHz locking range and a 55 Gb/s PRBS generator with a /50/55 /49sequence length. The circuits were fabricated in a SiGe BiCMOS technology with /61/49 /50 /48GHz. Corresponding mea- surement results validate the proposed design style and establish it as a viable alternative to emitter-coupled logic in high-speed applications. Both circuits operate from a 2.5 V nominal power supply and consume 650 mW and 550 mW, respectively.