← 返回 JSSC 论文列表JSSC 2006第9期Data Converters0.35μm BiCMOSPipeline ADCNeural Network Accelerator
A 100-dB SFDR 80-MSPS 14-Bit 035- 22m BiCMOS Pipeline ADC
本文介绍了一种在0.35微米BiCMOS工艺下实现的14位80MSPS ADC，具有100dB SFDR和1.2W功耗。
14-bit, 80-MSPS, 100-dB SFDR, 1.2 W, 3.3 V/5.0 V
ADCBiCMOS高动态范围校准技术电容重排
▸无专用采样保持电路的前端采样设计
▸采用BiCMOS开关输入缓冲器
▸结合校准和电容重排技术优化线性度
Abstract
This paper describes a 14-bit 80-MSPS ADC with
100-dB SFDR at 70-MHz input frequency in a 0.35-
m single-well
BiCMOS technology drawing 1.2 W from a dual 3.3 V/5.0 V
supply. Key barriers to high dynamic range in pipeline ADCs at
high clock rates and some methods to overcome these barriers will
be presented. These methods include a sampling front-end without
the use of a designated Sample and Hold (S/H). A BiCMOS
switching input buffer is used along with the strategic use of
BiCMOS design techni