JSSC 2006第9期Clocking & PLLs0.13μmCDR

A 125-Gbs Parallel Phase Detection Clock and Data Recovery Circuit in 013-22m CM

提出一种并行相位检测时钟数据恢复电路，提升线性CDR速度。

0.13μm CMOS, 12.5Gb/s, 0.56UI相位线性响应区域

时钟数据恢复并行相位检测电荷泵带宽扩展抖动容限

▸创新点1：并行相位检测器通过半速率时钟扩展UP脉冲宽度，解决了传统CDR中UP脉冲过短导致的速度限制问题，显著提升了相位检测的响应速度（方法创新）。

▸创新点2：采用不平衡电荷泵设计，优化了电荷泵的电流匹配特性，从而改善了CDR的相位线性响应区域，扩展至0.56UI（电路创新）。

▸创新点3：通过并联峰化和电容耦合技术，将决策锁存器的带宽扩展了1.7倍，提升了高频信号的恢复能力（电路创新）。

▸创新点4：整体系统在0.13μm CMOS工艺下实现了12.5Gb/s的高速数据传输，并在4-8MHz抖动频率下表现出超过0.5UIpp的抖动容限（系统创新）。

Abstract

A clock and data recovery (CDR) architecture fea- turing a parallel phase detector is proposed for speeding up linear-type CDRs. A cause of speed limit in conventional CDRs is very short UP pulses in its phase detector circuit. The parallel phase detector expands UP pulsewidth by adding ﬁxed-width using a half-rate clock. The parallel phase detector is used in the CDR with a couple of unbalanced charge-pump. The bandwidth of decision latches of the PD is extended by 1.7 times by using both shunt