JSSC 2006第9期Data Converters0.35μm

A Distortion Compensating Flash Analog-to-Digital Conversion Technique Venkata S

提出一种补偿静态非线性的高速高线性度闪存ADC设计技术。

160 MSPS, 6-bit, 50 mW, 3.3 V, 5.3 ENOB

闪存ADC静态非线性补偿高速高线性度背景比较器偏移校正过量量化噪声

▸补偿前端采样保持电路的静态非线性

▸新型背景比较器偏移校正方案

▸推导背景自零过程产生的过量量化噪声

Abstract

We present a ﬂash ADC design technique that com- pensates for static nonlinearity of the up-front track-and-hold circuit, so that high speed and high linearity can be obtained at the same time. The proposed technique functions in synergy with a new background comparator offset correction scheme. The excess quantization noise generated due to the background autozero process is derived. We demonstrate the efﬁcacy of our techniques with measurement results for a 160 MSPS 6-bit ﬂash converter design