Nanowatt, Sub-nS OTAs, With Sub-10-mV Input Offset, Using Series-Parallel

Abstract

In this paper, series-parallel (SP) current-division will be employed for the design of very low transconductance OTAs. From the theory and measurements, it will be shown that SP mir- rors allow the division of currents with division factors of thou- sands, without reducing matching or noise performance. SP mir- rors will be applied to the design of OTAs ranging from 33 pS to a few nS, with up to 1 V linear range, consuming in the order of 100 nW, and with a reduced area. An integrated 3.3-s time-constant integrator will also be presented. Several design concerns will be studied: linearity, offset, noise, and leakages, as well as layout tech- niques. A final comparative analysis concludes that SP association of transistors allows the design of very efficient transconductors, for demanding applications in the field of implantable electronics, among others.