A 62-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization

Abstract

A pipelined single-precision floating-point multiply- accumulator (FPMAC) featuring a single-cycle accumulate loop using base 32 and internal carry-save arithmetic with delayed addition is described. A combination of algorithmic, logic, and cir- cuit techniques enables multiply-accumulate operations at speeds exceeding 3 GHz with single-cycle throughput. The optimizations allow removal of the costly normalization step from the critical accumulate loop. This logic is conditionally powered down usi