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Direct Digital Synthesizer With Sine-Weighted DAC at 32-GHz Clock Frequency in InP DHBT Technology
采用InP DHBT技术的32GHz时钟频率直接数字频率合成器，通过正弦加权DAC架构实现高效能低功耗。
32GHz时钟频率，125MHz至16GHz输出范围，9.45W功耗
直接数字频率合成器正弦加权DACInP DHBT技术高频操作低功耗
▸创新点1：正弦加权DAC架构消除ROM需求（方法创新）。该设计通过正弦加权DAC直接实现相位到幅度的转换，无需传统DDS中的ROM查找表，简化了电路结构并降低了功耗。
▸创新点2：支持32GHz高频操作（系统创新）。该DDS在InP DHBT技术下实现了高达32GHz的时钟频率，突破了传统DDS的频率限制，适用于高频应用场景。
▸创新点3：低功耗设计（电路创新）。通过优化架构和电路设计，该DDS在32GHz时钟频率下仅消耗9.45W功率，显著降低了高频操作中的能耗。
▸创新点4：宽频率范围输出（系统创新）。该DDS能够在125MHz至16GHz范围内以125MHz步进生成正弦波输出，提供了灵活的频率合成能力。
Abstract
A direct digital synthesizer (DDS) implemented in InP double heterojunction bipolar transistor (DHBT) technology is reported. This DDS uses a sine-weighted digital to analog converter (DAC) architecture that eliminates the need for a ROM. This en- ables operation at high frequencies with lower power consumption compared to traditional approaches. The phase accumulator is 8-bits wide and the sine-weighted DAC uses the five most significant bits (MSBs) for phase to amplitude conversion. The DDS operates up to a 32-GHz clock frequency for all frequency control words (FCWs) and can synthesize sine-wave outputs from 125 MHz to 16 GHz in 125-MHz steps. The spurious free dynamic range (SFDR) is measured over the Nyquist bandwidth to be 31.00 dBc for the fundamental output frequency of 125 MHz. Over the full range of FCWs, the worst case SFDR is 21.56 dBc at an FCW of 95, and the average SFDR is 26.95 dBc. The circuit is implemented with 1891 transistors and consumes 9.45 W of power.