InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s

Abstract

In this paper, a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is intended for use in 80 Gbit/s optical fiber links, is pre- sented. The integrated circuit (IC) is manufactured using an in-house InP double heterostructure bipolar transistor (DHBT) technology, exhibiting cut-off frequency values of more than 220 GHz for both and /109/97/120. The CDR circuit in the topology of a phase-locked loop (PLL) is mainly composed of a half-rate linear phase detector including a 1:2 demultiplexer (DEMUX), a loop filter, and a voltage-controlled oscillator (VCO). Hence, the corresponding architecture of each of these components as well as the applied circuit design technique are extensively addressed. Concerning the performance achieved by the CDR/DEMUX IC, the recovered and demultiplexed 40 Gbit/s data from an 80 Gbit/s input signal feature clear eye opening with a signal swing as high as 600 mV /112/112. The extracted 40 GHz clock signal shows a phase noise as low as 98 dBc Hz at 100 kHz offset frequency. The cor- responding rms jitter amounts to 0.37 ps while the peak-to-peak jitter is as low as 1.66 ps. At a single supply voltage of 4.8 V, the power consumption of the full CDR/DEMUX IC amounts to 1.65 W. To the authors’ best knowledge, this work demonstrates the first CDR circuit at the achieved data rate, regardless of all the competing semiconductor technologies.