← 返回 JSSC 论文列表JSSC 2006第11期RF & Wireless0.18μm
A Low-Power Digital IC Design Inside the Wireless Endoscopic Capsule Xiang Xie G
无线内窥镜胶囊中的低功耗数字IC设计，用于实时图像监测和消化道诊断。
0.18μm CMOS, 6.2mW, 8fps@320×288, 2Mb/s
无线内窥镜低功耗IC时钟管理图像压缩VLSI架构
▸三阶段时钟管理架构节省46%功耗
▸可停止环形晶体振荡器实现60μW睡眠功耗
▸基于Bayer格式的新型图像压缩算法
Abstract
This paper proposes an architecture of the wireless
endoscopy system for the diagnoses of whole human digestive
tract and real-time endoscopic image monitoring. The low-power
digital IC design inside the wireless endoscopic capsule is discussed
in detail. A very large scale integration (VLSI) architecture of
three-stage clock management is applied, which can save 46%
power inside the capsule compared with the design without such a
low-power design. A stoppable ring crystal oscillator with minima