A New On-Chip Substrate-Coupled Inductor Model Implemented With

Abstract

Accurate modeling of the on-chip inductor is essential for the design of high-speed, low-power, and low-noise radio-fre- quency integrated circuits. The conventional model has a measur- able discrepancy as the current flowing in the substrate is not cor- rectly considered. The substrate-coupled inductor model, however, considers the losses generated in both the vertical and horizontal directions. This model gives an intelligent explanation of the re- duction in equivalent resistance between terminals with increasing frequency as well as the inductance and quality factor ( -factor). In order to implement a fully scalable model, the circuit elements in the substrate-coupled inductor model are expressed as monomial equations in terms of physical geometry. These equations consider the physical implications of the parameters as well as employing a mathematical fit for extrapolation. Measurements are made on in- ductors fabricated using a standard 0.35- m CMOS process and a 0.15- m silicon-on-insulator CMOS process to successfully verify this model.