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JSSC 2006第11期RF & Wireless0.35μm CMOS/0.15μm SOI CMOS

A New On-Chip Substrate-Coupled Inductor Model Implemented With Scalable Express

提出了一种新的片上衬底耦合电感模型,通过可扩展表达式实现精确建模。
高频下终端间等效电阻降低、电感及品质因数的智能解释
片上电感衬底耦合可扩展模型射频集成电路品质因数
考虑了衬底电流的垂直和水平方向损耗
采用单项式方程表达电路元件与物理几何关系
验证了模型在0.35μm CMOS和0.15μm SOI CMOS工艺中的适用性
Abstract
Accurate modeling of the on-chip inductor is essential for the design of high-speed, low-power, and low-noise radio-fre- quency integrated circuits. The conventional model has a measur- able discrepancy as the current flowing in the substrate is not cor- rectly considered. The substrate-coupled inductor model, however, considers the losses generated in both the vertical and horizontal directions. This model gives an intelligent explanation of the re- duction in equivalent resistance between termi