← 返回 JSSC 论文列表JSSC 2006第11期Clocking & PLLs0.18μmClock Generation
A Quantization Noise Suppression Technique for /1/6Fractional-/78Frequency Synthesizers
本文首次实现了一种用于1/6分数频率合成器的量化噪声抑制技术，采用1/1.5分频单元减小频率步进，降低量化噪声6dB。
0.18μm CMOS, 47.8mW, 100dBc/Hz@10kHz, 124dBc/Hz@1MHz, <1Hz频率分辨率, <10μs锁定时间
量化噪声抑制分数频率合成器1/1.5分频单元WLAN 802.11aWiMAX 802.16e
▸首次实现1/6分数频率合成器的量化噪声抑制技术
▸采用1/1.5分频单元减小频率步进
▸量化噪声降低6dB
Abstract
The first circuit implementation of quantization noise suppression technique for /1/6 fractional- frequency synthe- sizers using reduced step size of frequency dividers is presented in this paper. This technique is based on a 1/1.5 divider cell which can reduce the step size of the frequency divider to 0.5 and thus the reduced step size suppresses the quantization noise by 6 dB. This frequency synthesizer is intended for a WLAN 802.11a/WiMAX 802.16e transceiver. This chip is implemented in a 0.18- m CMOS process and the die size is 1.23 mm 0.83 mm. The power con- sumption is 47.8 mW. The in-band phase noise of 100 dBc/Hz at 10 kHz offset and out-of-band phase noise of 124 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The frequency resolution is less than 1 Hz and the lock time is smaller than 10 s.