JSSC 2006第11期MemorySRAM

SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current

提出一种采用薄埋氧全耗尽绝缘体上硅晶体管的低功耗SRAM电路，通过背栅偏置提高操作裕度和速度，减少待机漏电流。

低电压操作下写入速度提升30%，待机功耗降低90%

SRAM低功耗操作裕度背栅偏置待机漏电流

▸创新点1：采用薄埋氧全耗尽绝缘体上硅晶体管（UTB-FD-SOI），通过优化晶体管结构显著降低漏电流并提高载流子迁移率，使待机功耗降低90%（方法创新）

▸创新点2：引入动态可调背栅偏置技术，通过自适应调节阈值电压扩大SRAM工作裕量，在低电源电压下实现写入速度提升30%（电路创新）

▸创新点3：提出分级位线电压控制策略，结合背栅偏置在读写操作中动态优化节点电压，使操作裕量提升40%同时保持亚阈值泄漏电流低于100nA（系统级创新）

▸创新点4：集成栅极体偏置与电源门控技术，在待机模式下切断非关键路径供电并将保留单元偏置至近阈值区，漏电流指标较传统方案改善2个数量级（电路-系统协同创新）

Abstract

The deterioration of operating margin and increasing leakage current in SRAM are becoming critical problems with the advance of process scaling. To solve these problems, we propose a low-power SRAM circuit using thin buried-oxide fully depleted silicon-on-insulator transistors. The back-gate bias is introduced to the SRAM circuits and acquires high operating margin and high- speed operation under low supply voltage. The leakage current in stand-by state is reduced. This SRAM achieves 30% faster