← 返回 JSSC 论文列表JSSC 2006第12期Data Converters0.13μm CMOSTime-Interleaved ADC
A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture
提出一种消除时序偏移的高带宽时间交错ADC架构，实现1GS/s 11-bit 55dB SNDR性能。
1GS/s 11-bit 55dB SNDR 250mW 3.5mm²
时间交错ADC时序偏移消除Nyquist采样子采样结构高速ADC
▸采用Nyquist速率采样开关消除时序偏移
▸子采样双采样保持级联结构
▸特殊时钟方案降低采样开关负载
Abstract
A time-interleaved ADC architecture that eliminates the need to correct timing offsets and is yet scalable to high sampling rates is presented. To eliminate timing skews, a Nyquist rate sampling switch is used, which is followed by subsampled, double-sampled time-interleaved sample-and-hold (S/H) stages. This circuit is configured with a special clocking scheme that reduces the loading of the interleaved S/Hs on the Nyquist rate sampling switch, making this scalable to high sampling rates. The subsampled ADCs (sub-ADCs) in this design use a 3.5-bit/stage pipelined architecture. This 1-GS/s 11-bit ADC achieves 55-dB peak SNDR, 58.6-dB SNR, consumes 250-mW core power, and occupies a core area of 3.5 mm /50. This circuit is implemented in a dual-gate 1.2 V/2.5 V , 0.13- m logic CMOS process.