JSSC 2006第12期RF & Wireless90nmEqualizer

A 10-Gbs 5-Tap DFE4-Tap FFE Transceiver in 90-nm CMOS Technology

90纳米CMOS工艺下10Gb/s收发器，采用5抽头DFE和4抽头FFE实现高效信号传输

10Gb/s, 300mW, 1200mVppd

收发器决策反馈均衡器前馈均衡器CMOS高速通信

▸创新点1：5抽头决策反馈均衡器(DFE)采用1抽头推测性反馈和4抽头动态反馈的创新组合（方法创新），显著提高了对信道损耗的补偿能力，支持超过30 dB损耗的信道实现无误码传输。

▸创新点2：4抽头前馈均衡器(FFE)与DFE协同工作（系统创新），通过波特间隔优化设计，有效抵消信道失真和码间干扰，提升整体信号完整性。

▸创新点3：半速率架构在发射器和接收器中的全面应用（电路创新），降低了10-Gb/s高速操作下的功耗，同时保持时序精度，实现300 mW的低功耗表现。

▸创新点4：集成LC VCO的PLL设计（电路创新），为收发器提供低抖动时钟，确保高速数据传输的时序稳定性，进一步提升了系统性能。

Abstract

This paper presents a 90-nm CMOS 10-Gb/s trans- ceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feed- back equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ sig- naling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operatio