A 20-mW 640-MHz CMOS Continuous-Time /6/1ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

Abstract

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is imple- mented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time /6/1 mod- ulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive contin- uous-time /6/1ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The /6/1 ADC achieves 76-dB SNR, 78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT /6/1 modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply.