A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects

Abstract

This paper presents a clock-and-data recovery (CDR) for pseudo-synchronous high-density link applications. The CDR is a first-order bang-bang (BB) topology implemented in a stan- dard CMOS process and consists of a phase interpolator, a linear half-rate phase detector, an analog filter followed by a limiter and a digital loop filter operating at a reduced clock rate. A detailed BB CDR analysis derives the maximum tracking range, slew-rate limited jitter tolerance and maximum loop delay. The circuit is op- timized for high speed as well as low area and power consump- tion. The CDR operates from 8–28 Gb/s at a BER of 10 /49/50and tracks frequency deviations between the incoming data and the ref- erence clock of up to 122 ppm. The sinusoidal jitter tolerance is 0.35 UI/112/112for jitter frequencies 100 MHz and the total timing jitter of the recovered half-rate output data amounts to 0.22 UI/112/112 at a BER /6110 /49/50. The core CDR circuit occupies a chip area of 0.07 mm/50and consumes 98 mW from a 1.1-V supply.