← 返回 JSSC 论文列表JSSC 2006第12期Power Management0.25微米CDR
A 25-Gbs Multi-Rate 025- 22m CMOS Clock and Data Recovery Circuit Utilizing a Hy
一种0.25微米CMOS多速率时钟数据恢复电路，结合模拟/数字边界实现高性能、小面积和低功耗。
155Mb/s至2.5Gb/s, 197mA最大功耗, 5x5mm封装
时钟数据恢复多速率CMOSSigma-Delta频率捕获
▸采用混合型相位检测器和环路滤波器
▸无需参考频率的全数字频率捕获方法
▸集成相位-数字转换器和Sigma-Delta ADC
Abstract
A 0.25-
m CMOS, multi-rate clock and data recovery
(CDR) circuit that leverages unique analog/digital boundaries
in its phase detector and loop filter to achieve a fully integrated
CDR implementation with excellent performance, compact area,
and low power dissipation is presented. Key circuit blocks include
a phase-to-digital converter that combines a Hogge detector
with a continuous-time first-order Sigma-Delta analog-to-digital
converter, and a hybrid loop filter that contains an analog feedfor-