JSSC 2006第12期RF & Wireless0.13μmPower AmplifierNeural Network Accelerator

A /4331.5 dBm CMOS RF Doherty Power Ampliﬁer for

0.13微米CMOS工艺实现的差分Doherty功率放大器，最高输出功率4331.5dBm，峰值效率36%。

4331.5dBm输出功率, 36% PAE, 10dB功率范围内PAE>18%

Doherty功率放大器CMOS无线通信功率附加效率集总元件网络

▸创新点1：采用紧凑型集总元件网络替代传统传输线，通过被动阻抗逆变器实现空间节省和集成度提升，解决了传统Doherty功率放大器依赖笨重传输线的问题，实现了更高的芯片集成度。

▸创新点2：全差分结构设计显著提高了电路的抗干扰能力和信号完整性，特别适用于高频率无线通信场景，同时优化了功率附加效率（PAE）和输出功率。

▸创新点3：单芯片集成（除输出匹配电容和巴伦）通过0.13微米CMOS工艺实现，大幅减小了芯片尺寸（2.8x3.2 mm），同时保持了高性能（峰值PAE 36%，输出功率4331.5 dBm）。

▸创新点4：在GSM/EDGE信号下，通过优化设计满足严格的频谱掩模和误差矢量幅度（EVM）要求，实现了43325 dBm的输出功率和13%的峰值PAE，展现了出色的线性度和效率平衡。

Abstract

A fully differential Doherty power ampliﬁer (PA) is implemented in a 0.13- m CMOS technology. The prototype achieves a maximum output power of /4331.5 dBm with a peak power-added efﬁciency (PAE) of 36% (39% drain efﬁciency) with a GMSK modulated signal. The PAE is kept above 18% over a 10 dB range of output power. With a GSM/EDGE input signal, the measured peak output power while still meeting the GSM/EDGE mask and error vector magnitude (EVM) require- ments is /4325 dBm with a peak PAE of 13% (PAE is 6% at 12 dB back-off). Instead of using a bulky /52transmission line, a passive impedance inverter is implemented as a compact lumped-element network. All circuit components are fully integrated on a single CMOS die except for an off-chip capacitor for output matching and baluns. The die size is 2.8 3.2 mm/50including all pads and bypass capacitors.