A 5-GHz 108-Mb/s 2 2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm /80/49/100/66 Power Amplifiers in 90-nm CMOS

Abstract

Multiple antenna transceivers combined with MIMO signal processing offer the potential for increased data rates and/or range in wireless systems. This paper presents a fully integrated 5-GHz 2 2 MIMO WLAN transceiver RFIC imple- mented in 90-nm CMOS. The paper identifies the key MIMO integration issues and proposes techniques to optimize MIMO performance. It is shown that crosstalk between the multiple transceivers residing on the same die can degrade MIMO perfor- mance and has to be carefully minimized, especially when power amplifiers are integrated on-die. A shared LO generation and distribution network is designed to maximize MIMO phase noise immunity without introducing undesired crosstalk. The fabricated MIMO receiver achieves a sensitivity of 63 dBm while receiving 108 Mb/s in MIMO spatial multiplexing mode in the presence of a 25-ns Rayleigh fading channel. The sensitivity of a single receiver in the presence of A WGN noise is 76 dBm. Linearized 3.3-V 5-GHz power amplifiers with /80/49/100/66/61/50 /48 /53dBm deliver an average power of /43/49/51 /43/49 /54dBm each, in MIMO/SISO modes respectively /40EVM /61 /50/55 /50/53dB/41. The measured performance demonstrates the effectiveness of the isolation tech- niques employed. The system in a package includes an 18 mm /50 die and microstrip front-end matching networks implemented on a flip-chip package.