← 返回 JSSC 论文列表JSSC 2006第12期RF & Wireless0.13μmHigh-Speed Link
A 995113-Gbs XFP Transceiver in 013-22m CMOS
一款用于XFP模块的9.95-11.3Gb/s收发器，采用0.13μm CMOS工艺，满足XFP抖动规范。
0.13μm CMOS, 9.95-11.3Gb/s, 800mW
XFP收发器CMOS双环DLL/PLL二进制相位检测器抖动均衡
▸双环DLL/PLL结构
▸二进制相位检测器
▸半速率二进制相位检测器与2:1串行器实现全速率I/O
Abstract
A 9.95–11.3-Gb/s transceiver in 0.13-
m CMOS for
XFP modules is presented. The CDR uses a dual-loop DLL/PLL
with a binary phase detector to exceed XFP jitter specifications.
The dual loop solves the problem of having a controlled jitter
transfer bandwidth with a binary phase detector. A half rate bi-
nary phase detector with a 2:1 serializer implements full-rate I/O.
Dispersion jitter from 12
of FR4 is equalized resulting in system
JGEN under 4 mUI /82/77/83and 35 mUI /80/80. Power consumption i