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A Complex Image Rejection Circuit With Sign
提出一种基于符号检测的复杂图像抑制电路，用于直接转换接收机中的图像抑制。
65 dB图像抑制, 40 MS/s采样率, 23 mW功耗, 1.8 V电压
图像抑制直接转换接收机符号检测混合实现CMOS
▸创新点1：零强制符号自适应反馈算法（方法创新） - 提出了一种新型的零强制符号自适应反馈算法，通过符号检测实现图像抑制，显著降低了传统算法中的计算复杂度，适用于实时信号处理。
▸创新点2：仅检测四个符号更新增益和相位误差（方法创新） - 利用复数信道的正交特性，仅需检测四个符号即可更新增益和相位误差，大幅减少了硬件开销和功耗，提升了系统效率。
▸创新点3：混合形式实现图像抑制（系统创新） - 采用数字和模拟混合形式实现图像抑制，结合了数字误差检测器和模拟采样保持电路，实现了65 dB的高图像抑制比，同时采样速率达到40 MS/s。
▸创新点4：低功耗与高集成度（电路创新） - 原型芯片在0.18微米CMOS工艺下实现，面积仅为800x450微米，功耗23 mW，展现了高集成度和低功耗的优势，适用于便携式设备。
Abstract
In direct-conversion receivers, radio frequency (RF) signals are down-converted to low or zero intermediate frequency (IF) using complex in-phase and quadrature ( ) mixers with no prior image filtering. Due to path gain and phase errors, image leaks into the signal band during the down-conversion process. A generic image rejection algorithm is proposed to reject image in the baseband using a zero-forcing sign-sign adaptive feedback concept. The orthonormal property of complex channels is exploited to update their gain and phase errors by detecting only four signs, and image is corrected with four mul- tiplications and two additions. The proposed image rejection algorithm can be implemented in a digital, analog, or hybrid form. A complex baseband sample and hold (S/H) with a digital error detector, which is a hybrid example, achieves an image rejection of 65 dB while sampling at 40 MS/s. The prototype chip fabricated in 0.18- m CMOS occupies 800 450 m/50, and consumes 23 mW at 1.8 V.