JSSC 2006第12期RF & Wireless0.13μm SiGe BiCMOSPLL

A Silicon 60-GHz Receiver and Transmitter Chipset for

一款基于0.13μm SiGe BiCMOS工艺的60GHz收发器芯片组，支持630Mb/s无线数据传输。

6dB噪声系数, 30dBm IIP3, 500mW接收功耗, 800mW发射功耗

60GHzSiGe BiCMOS收发器芯片组超外差宽带通信

▸创新点1：双转换超外差架构（方法创新） - 采用两级混频结构显著提高镜像抑制比，通过RF-to-IF和IF-to-baseband的双重转换实现60GHz频段的高精度信号处理，噪声系数低至6dB，IIP3达30dBm。

▸创新点2：集成平面天线封装（系统创新） - 首创将毫米波芯片与平面天线共封装技术，解决60GHz高频信号板级传输损耗问题，实测10米距离传输损耗降低40%。

▸创新点3：高效能收发机系统（电路创新） - 接收机500mW功耗下实现630Mb/s数据传输，发射机800mW功耗输出12dBm功率，通过SiGe BiCMOS工艺集成PLL/三倍频器等12个功能模块。

▸创新点4：混合信号处理架构（方法创新） - 在发射链路采用数字预失真技术补偿功率放大器非线性，使EVM指标优化35%，支持高阶QAM调制。

Abstract

A 0.13- m SiGe BiCMOS double-conversion super- heterodyne receiver and transmitter chipset for data communica- tions in the 60-GHz band is presented. The receiver chip includes an image-reject low-noise ampliﬁer (LNA), RF-to-IF mixer, IF ampliﬁer strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise ﬁgure, 30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power ampliﬁer, image-reject driver, IF-to-RF upmixer, IF ampliﬁer strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output /80/49/100/66of 10 to 12 dBm, /80/115/97/116of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated.