A 125 /22W, Fully Scalable MPEG-2 and H.264/A VC Video Decoder for

Abstract

A low-power dual-standard video decoder has been developed for mobile applications. It supports MPEG-2 SP@ML and H.264/A VC BL@L4 video decoding in a single chip and fea- tures a scalable architecture to reach area/power efficiency. This chip integrates diverse algorithms of MPEG-2 and H.264/A VC to reduce silicon area. Three low-power techniques are proposed. First, a domain-pipelined scalability (DPS) technique is used to optimize the pipelined structure according to the number of processing cycles. Second, bandwidth scalability is implemented via a line-pixel-lookahead (LPL) scheme to improve the external bandwidth and reduce the internal memory size, leading to 51% of memory power reduction compared to a conventional design. Third, low-power motion compensation and deblocking filter are designed to reduce the operating frequency without degrading system performance. A test chip is fabricated in a 0.18 m one-poly six-metal CMOS technology with an area of 15.21 mm /50. For mobile applications, H.264/A VC and MPEG-2 video decoding of quarter-common intermediate format (QCIF) sequences at 15 frames per second are achieved at 1.15 MHz clock frequency with power dissipation of 125 W and 108 W, respectively, at 1 V supply voltage.