← 返回 JSSC 论文列表JSSC 2007第1期RF & Wireless0.18μm
A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago
一款1 Tb/s 3W的3D堆叠芯片间时钟与数据电感耦合收发器。
1 Tb/s, 3 W, 1 GHz时钟速率, 1 Gb/s每通道, BER低于10^-12
电感耦合3D堆叠双相调制时分多址高数据速率
▸创新点1：采用双相调制(BPM)技术显著提升数据链路的抗噪性能，通过差分信号处理有效抑制共模噪声，在1 GHz时钟频率下实现BER低于10^-12的可靠传输。
▸创新点2：提出四相时分多址(TDMA)架构，通过时间域隔离降低1024通道并行传输时的串扰，使系统在30μm间距高密度布局下仍保持BER优于10^-11。
▸创新点3：实现10μm超薄芯片堆叠厚度，通过优化电感耦合器结构和3D集成工艺，在2mm²面积内集成1024数据收发器+16时钟收发器，功耗仅3W。
▸创新点4：开发新型高密度布局方案，在1mm/50单元面积内实现30μm间距的收发器阵列排布，相比传统方案集成度提升5倍。
Abstract
A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 m in a layout area of 1 mm /50. The total layout area including 16 clock transceivers is 2 mm /50in 0.18 m CMOS and the chip thickness is reduced to 10 m. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, re- ducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than /49/48 /49/51.