A 380 MHz Direct Digital Synthesizer/Mixer With Hybrid CORDIC Architecture in 0.25 /22m CMOS

Abstract

The paper describes the implementation of a 380 MHz, 13 bit, direct digital synthesizer/mixer IC in 0.25 m CMOS technology. The circuit employs an innovative archi- tecture which divides the /52rotation operation required in the quadrature synthesizer/mixers, in three rotations. The first two rotations are implemented by using a CORDIC datapath completely realized in carry-save arithmetic. The directions of the CORDIC rotations are computed in parallel by using a little lookup table, for the first rotation, and a multiply by constant and addition circuit for the second rotation. The final (third) rotation is multiplier-based, in order to reduce the circuit latency and increase the circuit performances. The CORDIC datapath is implemented with a novel approach both at the algorithmic level and at the transistor level. At the al- gorithmic level the combined employ of sign-extension prevention, overflow prevention and a novel rounding scheme are presented. At the transistor level a design style that jointly uses full-CMOS and DPL to improve the circuit latency is described. The overall circuit performances are very interesting. The syn- thesizer/mixer IC, realized in a 0.25 m CMOS technology, has an area occupation of 0.22 mm /50and dissipates 152 mW at 380 MHz with a supply voltage of 2.5 V.