← 返回 JSSC 论文列表JSSC 2007第1期Memory56nmFlash Memory
A 56-nm CMOS 99-mm/508-Gb Multi-Level NAND Flash Memory With 10-MB/s
56纳米CMOS工艺的8Gb NAND闪存，实现10MB/s编程速度和98.8mm²芯片面积
56nm CMOS, 3.3V, 10MB/s, 98.8mm²
NAND闪存CMOS编程速度芯片面积噪声消除
▸创新点1：单边行解码器和页缓冲器布局（方法创新） - 通过优化芯片布局，采用单边行解码器和单边页缓冲器设计，显著提高了芯片面积利用率至70%，同时减少了布线复杂度，实现了更紧凑的芯片尺寸（98.8 mm²）。
▸创新点2：8kB页大小提升编程吞吐量（系统创新） - 将页大小从4kB增加到8kB，使编程吞吐量提升至10 MB/s，达到与二进制存储器相当的性能，显著提高了数据写入效率。
▸创新点3：噪声消除电路和双线方案（电路创新） - 引入噪声消除电路和双线（dual-line）方案，有效降低了信号干扰，同时兼顾了芯片尺寸的小型化和编程速度的提升，实现了高性能与高可靠性的平衡。
▸创新点4：外部页复制技术（系统创新） - 采用外部页复制技术，实现了93毫秒的快速块复制，通过优化1 MB块大小的使用，进一步提高了数据管理的效率和速度。
Abstract
A single 3.3-V only, 8-Gb NAND flash memory with the smallest chip to date, 98.8 mm /50, has been successfully devel- oped. This is the world’s first integrated semiconductor chip fab- ricated with 56-nm CMOS technologies. The effective cell size in- cluding the select transistors is 0.0075 m/50per bit, which is the smallest ever reported. To decrease the chip size, a very efficient floor plan with one-sided row decoder, one-sided page buffer, and one-sided pad is introduced. As a result, an excellent 70% cell area efficiency is realized. The program throughput is drastically im- proved to twice as large as previously reported and comparable to binary memories. The best ever 10-MB/s programming is realized by increasing the page size from 4 kB to 8 kB. In addition, noise cancellation circuits and the dual /68/68-line scheme realize both a small die size and a fast programming. An external page copy achieves a fast 93-ms block copy, efficiently using a 1-MB block size.