← 返回 JSSC 论文列表JSSC 2007第1期Clocking & PLLs0.15μm CMOS
All Digital Spread Spectrum Clock Generator for EMI Reduction Simon Damphousse, Khalid Ouici, Ahmed Rizki, and
采用全数字延迟线实现电磁干扰抑制的扩频时钟发生器
27MHz时钟, 13dB峰值抑制, 3%频偏, 100kHz调制, 7.1mW功耗
扩频时钟电磁干扰抑制数字延迟线实时校准三角波调制
▸全数字延迟线(DDLi)实现扩频调制
▸实时数字校准电路保证工艺/温度稳定性
▸三角波调制实现上下扩频功能
Abstract
An effective solution to control electromagnetic inter- ference in computing appliances such as DVD players or home the- ater systems is to apply modulation on the system clock. The pres- ence of modulation on the clock reduces the radiated power per unit bandwidth. We present the implementation of a spread spec- trum clock generator (SSCG) using strictly digital components. A digital delay line (DDLi) controlled by a small digital circuit is used to increase or decrease the delay on a clock and hence create a mod- ulated output. The DDLi total electrical length is no longer than one period of the 27-MHz reference clock as the digital circuit can adjust to the limited length of the line. The circuit can produce up or down spread by modulating the frequency of the reference with a triangular waveform. The measured peak power reduction is greater than 13 dB for a deviation of about 3% and a frequency modulation of 100 kHz. A real-time digital calibration circuit en- ables a process and temperature independent operation. The cir- cuit occupies 0.06 mm /50in a 0.15- m CMOS process and consumes 7.1 mW.