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A 630 MHz, 76 mW Direct Digital Frequency Synthesizer Using Enhanced ROM
提出一种基于MTM的DDFS设计，优化ROM压缩算法，实现高时钟频率和低功耗。
0.25μm, 2.5V, 630MHz, 76mW
直接数字频率合成器MTMROM压缩低功耗高时钟频率
▸创新点1：基于MTM的ROM压缩优化算法（方法创新）。提出了一种新颖的算法，用于寻找最优MTM分解，在保证目标无杂散动态范围（SFDR）90 dBc的同时最小化ROM大小，显著提高了存储效率。
▸创新点2：双触发器拓扑结构实现低功耗（电路创新）。通过采用两种不同功耗和延迟特性的触发器拓扑结构，结合电源驱动综合技术，实现了低功耗设计，在1.8V电源下功耗低至24.9 mW。
▸创新点3：高时钟频率设计（系统创新）。通过优化ROM压缩和简化多操作数加法器结构，实现了630 MHz的高时钟频率操作，同时保持76 mW的较低功耗。
▸创新点4：电源电压可调设计（电路创新）。支持2.5V和1.8V两种电源电压模式，在430-630 MHz频率范围内灵活平衡性能与功耗，适应不同应用场景需求。
Abstract
The paper presents a detailed description of a direct digital frequency synthesizer (DDFS) based on a Multipartite Table Method (MTM) which is a salient lookup table compression technique. A novel algorithm to find the optimal MTM decom- position which minimizes the ROM size while archiving a target spurious free dynamic range (SFDR) is presented in the paper. The DDFS designed with the proposed technique is ideally suited for a high clock frequency operation, requiring small lookup tables and simple multi-operand adders. Low-power operation is achieved through a power-driven syn- thesis, by using in the circuit two flip-flop topologies (with different power and delay performances). A test chip has been realized in 0.25 m, 2.5 V technology. The circuit achieves a 90 dBc SFDR and operates at a maximum clock frequency of 630 MHz, with 76 mW power dissipation. By re- ducing the power supply at 1.8 V , a maximum operating frequency of 430 MHz was measured, with a total power dissipation as low as 24.9 mW.