A 63 dB SNR, 75-mW Bandpass RF /6/1ADC at 950 MHz Using 3.8-GHz Clock in 0.25- /22m SiGe BiCMOS Technology

Abstract

A fourth-order continuous-time LC bandpass sigma- delta ADC is designed using a new architecture with only non-re- turn-to-zero feedback DACs to mitigate problems associated with clock jitter, along with individual control of coefficients in the noise transfer function. The ADC performs direct digitization of RF sig- nals around 950-MHz center frequency with a 3.8-GHz clock. The operation of the proposed ADC architecture is examined in detail and extra design parameters are introduced to enhance the oper- ating range and improve the stability of the ADC. Measurement results of the ADC, implemented in IBM 0.25- m SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz and 1 MHz, respectively, around 950 MHz, while con- suming 75 mW of power from 1.25-V supply.