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A 90-nm Wideband Merged CMOS LNA and Mixer Exploiting
采用90nm CMOS技术设计的宽带合并LNA和混频器芯片，适用于软件定义无线电接收机。
12.1 dB功率转换增益，8.4 dB噪声系数，9.8 mW功耗
宽带LNA混频器噪声消除CMOS软件定义无线电
▸创新点1：噪声消除技术（方法创新） - 通过创新的噪声消除电路设计，有效降低了系统的噪声系数，最小单边带噪声系数达到8.4 dB，显著提升了接收机的灵敏度。
▸创新点2：宽带设计（系统创新） - 覆盖0.1至3.85 GHz的超宽带频率范围，S11低于-10 dB，适用于软件定义无线电（SDR）应用，展现了卓越的频率适应性。
▸创新点3：低功耗集成（电路创新） - 采用90-nm CMOS工艺，核心功耗仅为9.8 mW，电源电压1.2 V，实现了高集成度和低功耗的完美结合，适合便携式设备。
▸创新点4：高增益与线性度（性能创新） - 功率转换增益达到12.1 dB，输入1 dB压缩点为-12.8 dBm，在宽频带内保持了优异的信号处理能力。
Abstract
This paper describes the design and implementation of a wideband merged LNA and mixer chip covering the frequency range from 0.1 to 3.85 GHz using 90-nm CMOS technology. Its high level of integration as well as its low power consumption makes it suitable for the rapidly growing software defined radio RF receivers. The chip performance achieves S11 below 10 dB along the entire band and a minimum single side band noise figure of 8.4 dB at IF frequency of 70 MHz. Power conversion gain is measured to be 12.1 dB while the input referred 1 dB compression point is measured to be 12.8 dBm. The chip core consumes only 9.8 mW from a 1.2 V supply with a die area, including the pads, of 0.88 mm /50.