← 返回 JSSC 论文列表JSSC 2007第2期Analog Circuits0.35μm
A Low-Power Floating-Gate-MOS-Based CDMA Matched Filter Featuring Coupling
基于浮栅MOS技术的低功耗CDMA匹配滤波器，通过单步匹配和耦合电容断开实现低功耗和高增益。
0.35μm CMOS, 2.5V, 8 Mchip/s, 5.3mW
低功耗CDMA匹配滤波器浮栅MOS耦合电容单步匹配
▸创新点1：采用浮栅MOS技术实现低功耗和紧凑设计（电路创新）。该技术通过电荷存储机制减少动态功耗，在0.35μm CMOS工艺下实现5.3mW@2.5V的低功耗表现，同时芯片面积仅1.0mm²。
▸创新点2：提出单步匹配操作架构（系统创新）。通过优化传统多级匹配流程，将相关运算简化为单次操作，显著降低系统复杂度并提升8Mchip/s处理速度。
▸创新点3：动态耦合电容断开技术（方法创新）。在非活跃匹配阶段切断无关电容连接，不仅降低50%无效功耗，还将输出增益提升近2倍。
▸创新点4：集成255-chip高容量匹配滤波器（系统创新）。通过电容阵列优化布局，在有限面积内实现长码匹配功能，支持CDMA系统的实时信号处理需求。
Abstract
A low-power and compact CDMA matched filter has been developed based on the floating-gate MOS technology. The low-power operation has been achieved by employing single-step matching and disconnection of coupling-capacitors not involved in each matching operation. The capacitance disconnection has also enhanced the output gain to almost double. The 255-chip matched filter fabricated in a 0.35- m CMOS technology demonstrated 5.3-mW operation at 2.5-V power supply and the chip rate of 8 Mchip/s, while occupying a chip area of 1.0 mm /50.