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An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL
提出一种敏捷的VCO频率校准技术，应用于10GHz CMOS PLL，实现快速频率调谐和低相位噪声。
10GHz, 102dBc/Hz@1MHz, <-48dBc参考杂散, 44mW低功耗模式, <4μs校准时间
压控振荡器锁相环频率校准CMOS相位噪声
▸创新点1：基于信号周期差的频率比较技术（方法创新）。该技术通过测量两个信号之间的周期差来实现快速频率比较，显著提高了校准速度，校准时间少于4微秒，适用于高频PLL应用。
▸创新点2：高效的VCO离散调谐曲线搜索方法（系统创新）。该方法通过智能搜索算法快速定位最优VCO调谐曲线，优化了频率覆盖范围和相位噪声性能，相位噪声达到-102 dBc/Hz @1MHz偏移。
▸创新点3：混合信号电路设计支持快速校准（电路创新）。设计了专用的混合信号电路来支持提出的校准技术，包括数字控制逻辑和模拟接口电路，实现了低功耗（44 mW）和高集成度。
▸创新点4：敏捷的VCO频率校准系统集成（系统创新）。将提出的校准技术与PLL系统无缝集成，在0.18微米CMOS工艺下实现了10 GHz工作频率，参考杂散低于-48 dBc。
Abstract
This paper reports an agile VCO frequency calibra- tion technique and its application on a 10-GHz CMOS integer- N phase-locked loop. The proposed calibration method accomplishes efficient search for an optimum VCO discrete tuning curve among a group of frequency sub-bands. The agility is attributed to a pro- posed frequency comparison technique which is based on mea- suring the period difference between two signals. Other mixed- signal circuits are also developed to facilitate this approach. The PLL incorporating the proposed calibration technique is imple- mented in a 0.18- m CMOS process. The measured PLL phase noise at 10 GHz is 102 dBc/Hz at 1-MHz offset frequency and the reference spurs are lower than 48 dBc. The PLL consumes 44 mW in the low-current mode. The calibration time is less than 4 s.