← 返回 JSSC 论文列表JSSC 2007第2期RF & Wireless0.18μmSAR ADC
Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver
提出一种双时间交织逐次逼近寄存器ADC，用于超宽带无线电，实现500MS/s采样率和低功耗。
500MS/s, 5-bit, 7.8mW
超宽带时间交织逐次逼近寄存器低功耗CMOS
▸创新点1：时间交织SAR架构（系统创新） - 该论文提出了一种时间交织的逐次逼近寄存器（SAR）架构，相较于传统的闪存架构，显著降低了比较次数，从指数级减少到线性级，从而实现了更高的能效。
▸创新点2：6路时间交织拓扑（电路创新） - 采用6路时间交织拓扑结构，使得每个ADC能够在500 MS/s的采样率下工作，同时通过全定制逻辑和自我定时的位循环技术，确保了高速度和低功耗的平衡。
▸创新点3：比较器预放大器占空比控制（电路创新） - 通过比较器预放大器的占空比控制，进一步优化了功耗，使得整个ADC在500 MS/s的采样率下仅消耗7.8 mW的功率，显著提高了能效。
▸创新点4：输出分辨率可调（系统创新） - 该ADC的输出分辨率可调至1位，提供了额外的功耗节省选项，使得系统在不同应用场景下能够灵活调整功耗和性能的平衡。
Abstract
Ultra-wideband radio requires Nyquist sampling rates of at least 500 MS/s with low resolutions. While flash is the traditional choice for these specifications, a comparative energy model is used to show the potential energy savings of the time-in- terleaved successive approximation register architecture, which requires only a linear number of comparisons versus exponential for flash. A dual 500-MS/s, 5-bit ADC chip is implemented in a 0.18- m CMOS process, with both ADCs synchronized for use in an I/Q UWB receiver. Each ADC uses a 6-way time-interleaved SAR topology with full custom logic, self-timed bit-cycling, and duty cycling of the comparator preamplifiers to enable 500-MS/s operation with 7.8 mW power consumption. The output resolution is adjustable down to the 1-bit level for additional power savings.