← 返回 JSSC 论文列表JSSC 2007第2期Digital Circuits0.35μm
VLSI Architecture of Line-Based Lifting Wavelet Transform for Motion JPEG2000
提出了一种用于Motion JPEG2000的线基提升小波变换VLSI架构，支持无损和有损操作。
0.35μm CMOS, 150MHz, 90,000 gates
VLSI架构提升小波变换Motion JPEG2000FPGAASIC
▸新型单元结构：提出了一种执行提升计算单元的新型细胞结构，通过详细分析提升算术的操作序列并施加因果关系进行硬件优化，显著提高了处理效率，支持(9,7)和(5,3)滤波器。
▸简单提升内核：通过重复排列单元细胞组织了一个新的简单提升内核，实现了对Motion JPEG2000的高效处理，支持任意尺寸瓦片和同时输出四种小波系数(LL, LH, HL, HH)。
▸高性能实现：该处理器在0.35微米CMOS工艺中实现，占用约90,000门，稳定工作在150 MHz，具有与输入相同的吞吐率，适用于实时图像处理。
▸多功能支持：支持有损和无损操作，分别通过(9,7)和(5,3)滤波器实现，提供了灵活的应用场景适应能力。
Abstract
In this paper, we proposed a new architecture of lifting processor for JPEG2000 and implemented it with both FPGA and ASIC. It includes a new cell structure that executes a unit of lifting calculation to satisfy the requirements of the lifting process of a repetitive arithmetic. After analyzing the operational sequence of lifting arithmetic in detail and imposing the causality to imple- ment in hardware, the unit cell was optimized. A new simple lifting kernel was organized by repeatedly arranging the unit cells and a lifting processor was realized for Motion JPEG2000 with the kernel. The proposed processor can handle any size of tiles and support both lossy and lossless operation with (9,7) filter and (5,3) filter, respectively. Also, it has the same throughput rate as the input, and can continuously output the wavelet coefficients of the four types (LL, LH, HL, HH) simultaneously. The lifting processor was implemented in a 0.35 m CMOS fabrication process, the re- sult of which occupied about 90 000 gates, and was stably operated in about 150 MHz.